So the code instructs the FPGA (or, more accurately, the Verilog compiler) to examine the number and set dispoutput based on the input. The <= character, by the way, are a non-blocking assignment.

Hence, it relieves the system’s CPU from the task of polling in a multi-level priority system. This paper deals with implementation of a priority interrupt controller using Verilog language.

I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects.